In recent years, an active matrix-type liquid crystal display device having a TFT (Thin Film Transistor) as a switching element is known. A display unit of an active matrix-type liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines (scanning signal lines), and a plurality of pixel formation portions provided at the intersections of the plurality of source bus lines and the plurality of gate bus lines. The pixel formation portions are disposed in a matrix to form a pixel array.
FIG. 16 is a circuit diagram showing the configuration of the pixel formation portion in the active matrix-type liquid crystal display device. As shown in FIG. 16, each pixel formation portion includes: a TFT 10 having a gate electrode 11 connected to a gate bus line GL passing a corresponding intersection and a source electrode 12 connected to a source bus line SL passing the intersection; a pixel electrode 14 connected to a drain electrode 13 of the TFT 10; a common electrode 16 and an auxiliary capacitance electrode 18 commonly provided for the plurality of pixel formation portions; a liquid crystal capacitance 15 formed by the pixel electrode 14 and the common electrode 16; and an auxiliary capacitance 17 formed by the pixel electrode 14 and the auxiliary capacitance electrode 18. A pixel capacitance Cp is formed by the liquid crystal capacitance 15 and the auxiliary capacitance 17. A voltage indicative of the pixel value is held in the pixel capacitance Cp based on a video signal which is received by the source electrode 12 of each of the TFT 10 from the source bus line SL when the gate electrode 11 of the TFT 10 receives an active scan signal from the gate bus line GL.
By the way, since the pixel electrode 14 and the source bus line SL are disposed in positions close to each other, as shown in FIG. 16, a parasitic capacitance 19 exists between the pixel electrode 14 and the source bus line SL. In a display device employing the line inversion drive scheme, the polarity of potential of the pixel electrode 14 with respect to the potential of the common electrode 16 is inverted every line. Consequently, when entire-surface uniform brightness display is performed, the potential of a video signal fluctuates every horizontal scanning period. At this time, due to the influence of the parasitic capacitance 19, fluctuations in potential occur also in the pixel electrode 14 connected to the pixel capacitance Cp in which data is already written. As a result, a stripe (line in the horizontal direction) may be visually recognized on the screen. This will be described below with reference to FIGS. 17 and 18. Note that in the following, when a component in a pixel formation portion provided at a intersection between a k-th (k denotes “1”, “2”, . . . or “even-numbered” or “odd-numbered”) gate bus line and an arbitrary source bus line is mentioned, it will be simply described as “(component name or the like) in the k-th line” (for example, “pixel electrode in an odd-numbered line”).
FIG. 17 is a signal waveform diagram in a certain frame (“even-numbered frame” in this case) and FIG. 18 is a signal waveform diagram in the following frame (“odd-numbered frame” in this case). Note that it is assumed that data is written to the final line in the period (horizontal scanning period) from time point t5 to time point t6, and the final line is an even-numbered line. With respect to the writing to the final line, it is assumed that writing of the positive polarity is performed in even-numbered frames, and writing of the negative polarity is performed in odd-numbered frames.
FIGS. 17A and 17B and FIGS. 18A and 18B show fluctuations in a potential VS of the source electrode 12 (hereinafter, referred to as a “source potential”) with respect to a ground potential GND. FIGS. 17C and 17D and FIGS. 18C and 18D show fluctuations in a potential Veven of the pixel electrode 14 in an even-numbered line (hereinafter, referred to as a “pixel potential”) with respect to a potential VCOM of the common electrode 16 (hereinafter, referred to as a “common electrode potential”). Further, FIGS. 17E and 17F and FIGS. 18E and 18F show fluctuations in a pixel potential Vodd of an odd-numbered line with respect to the potential VCOM of the common electrode 16. Note that a delay in the change in the potential at each time point is ignored for convenience of explanation.
First, attention is paid to an even-numbered frame. As shown in FIG. 17A, with respect to the source potentials VS, in a horizontal scanning period until time point t6, high potential and low potential appear alternately. In a vertical blanking period at the time point t6 and later, the source bus line SL is set to the high-impedance state. When data is written in an even-numbered line in the horizontal scanning period from time point t1 to time point t2, the pixel potential Veven in the even-numbered line changes as shown in FIG. 17C. Further, when data is written in an odd-numbered line in the horizontal scanning period from time point t2 to time point t3, the pixel potential Vodd in the odd-numbered line changes as shown in FIG. 17F. Note that the pixel potential Vodd in an odd-numbered line in the horizontal scanning period from time point t1 to time point t2 is on the positive polarity side with respect to the common electrode potential VCOM, but it is not shown for convenience of explanation.
When attention is paid to changes in the pixel potential Veven in an even-numbered line, after the horizontal scanning period in which data is written, the potential drops by ΔV from a target potential in the horizontal scanning period in which data is written in an odd-numbered line, and the potential rises to the target potential in the following horizontal scanning period, that is, a horizontal scanning period in which data is written in an even-numbered line. On the other hand, when attention is paid to changes in the pixel potential Vodd in an odd-numbered line, after the horizontal scanning period in which data is written, the potential rises by ΔV from the target potential in the horizontal scanning period in which data is written in an even-numbered line, and the potential drops to the target potential in the following horizontal scanning period, that is, a horizontal scanning period in which data is written in an odd-numbered line. Moreover, in a vertical blanking period after completion of writing to the final line, as described above, the source bus line is set to the high-impedance state. Consequently, when the final line is an even-numbered line, the pixel potential Veven of an even-numbered line in the vertical blanking period is maintained as the target potential, but the pixel potential Vodd in an odd-numbered line in the vertical blanking period is maintained as potential higher than the target potential by ΔV. Therefore, in the vertical blanking period, a voltage Ve applied to the liquid crystal in an even-numbered line is maintained as the target voltage, and a voltage Vo applied to the liquid crystal in an odd-numbered line is maintained as a voltage lower than the target voltage by ΔV. Note that in the case where the final line is an odd-numbered line, in the vertical blanking period, the voltage applied to the liquid crystal in an even-numbered line is maintained as a voltage lower than the target voltage by ΔV, and the voltage applied to the liquid crystal in an odd-numbered line is maintained as the target voltage.
Next, attention is paid to an odd-numbered frame. As shown in FIGS. 18A to 18F, the polarity of writing to an even-numbered line and the polarity of writing to an odd-numbered line are opposite to those in an even-numbered frame. However, also in the odd-numbered frame, in the vertical blanking period, the voltage Ve applied to the liquid crystal in an even-numbered line is maintained as a target voltage, and the voltage Vo applied to the liquid crystal in an odd-numbered line is maintained to be lower than the target voltage by ΔV.
As described above, in both of the even-numbered and odd-numbered frames, during the vertical blanking period, a voltage difference of ΔV occurs between the voltage Ve applied to the liquid crystal in an even-numbered line and the voltage Vo applied to the liquid crystal in an odd-numbered line. As a result, as described above, a stripe (line in the horizontal direction) is visually recognized.
As for this, Japanese Laid-open Patent Publication No. 2001-202066 discloses an invention of an image display device which suppresses occurrence of a stripe by supplying a video signal to a source bus line during the vertical blanking period. In addition, Japanese Laid-open Patent Publication No. 2005-62535 discloses an invention of a liquid crystal display device which prevents occurrence of display unevenness by providing a signal line selecting circuit for switching and connecting a plurality of signal lines to a single source bus line.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2001-202066    [Patent Document 2] Japanese Laid-open Patent Publication No. 2005-62535